Hi, I'm Theo!
Electrical engineering student at the University of Illinois Urbana-Champaign, focused on digital ASIC design, RTL verification, and半导体 engineering. Building toward a career designing the chips that power everything.
Featured Projects
View all →Custom AES-128 Hardware Accelerator
Designed an AXI4-Lite peripheral and IP core to accelerate AES-128 encryption/decryption on FPGA, controlled via microphone input and Python scripts.
SystemVerilogFPGAAXI4-LitePython
In ProgressRISC-V Pipelined Core — Coming Soon
Designing a 5-stage pipelined RISC-V RV32I core in SystemVerilog with hazard detection, forwarding, and a custom UVM testbench for verification.
SystemVerilogRISC-VUVMASIC Flow
Fab Power Distribution Dashboard
Streamlit + ML dashboard at Samsung Austin Semiconductor to quantify pressure stability improvements across 8 wafer-cleaning chambers.
PythonStreamlitMLDAQ
Get in Touch
Have a question or want to collaborate? Drop me a message.